When the signal of the circuit is transmitted, the strengths of PMOS and NMOS transistors in the circuit (such as a CMOS circuit) are unable to match mutually as a result of the process shift or the voltage variation, therefore, the transmission speeds of the logic 0 signal and logic 1 signal in the circuit are different, in other words, a logic signal is transmitted faster, and another logic signal is oppositely transmitted more slowly, so that the time skew will be existed in the circuit, which may limit the high-speed transmission performance of the circuit.
Referring to FIG. 1, there is shown a circuit diagram for compensating the time skew of circuit of the prior art. The prior art will take an input buffer 10 as an example, which comprises a current mirror 101, a comparator 103, and an inverter 105.
Wherein the current mirror 101 is connected to a first voltage (VDD), and consists of P1 and P2 PMOS transistors. The comparator 103 is connected to a second voltage (VSS), connected with the current mirror 101 at a first node 102 and a second node 104, and consists of N1 and N2 NMOS transistors. Besides, the first node 102 is connected to the gates of P1 and P2 transistors of the current mirror 101, and the second node 104 is further connected to the inverter 105.
The comparator 103 is used for receiving and comparing an input signal and a reference signal to generate a comparative result, the comparative result is transmitted to the input terminal of the inverter 105, and then inverted by the inverter 105, so as to output an output signal from the output terminal of the inverter 105.
The compensation method of the input buffer 10 of the prior art is described as following: if the element characteristics of N1 and N2 transistors are much stronger than P1 and P2 transistors, the logic 1 signal will be transmitted faster and outputted from the inverter 105, in other words, the raising edge of the logic 1 signal will be transmitted to the output terminal of the inverter 105 ahead of time.
Furthermore, the voltage on the first node 102 can be formed with a lower potential because N1 transistor is stronger; then, the VGS voltages of P1 and P2 transistors will be increased according to the first node 102 having the lower potential to promote the strengths of P1 and P2 transistors. Thus, the falling edge of the logic 0 signal will be transmitted faster and outputted from the inverter 105 ahead of time to compensate the raising edge of the logic 1 signal that is transmitted quickly by the NMOS transistor. Thereby, the time skew existed in the input buffer 10 can be reduced.
Oppositely, the element characteristics of N1 and N2 transistors are much weaker than P1 and P2 transistors, the logic 1 signal will be transmitted slower and outputted from the inverter 105, in other words, the raising edge of the logic 1 signal will be transmitted to the output terminal of the inverter 105 behind of time.
Furthermore, the voltage on the first node 102 can be formed with a higher potential because N1 transistor is weaker; then, the VGS voltages of P1 and P2 transistors will be decreased according to the first node 102 having the higher potential to decrease the strengths of P1 and P2 transistors. Thus, the falling edge of the logic 0 signal will be transmitted slower and outputted from the inverter 105 behind time to compensate the raising edge of the logic 1 signal that is transmitted slowly by the NMOS transistor. Thereby, the time skew existed in the input buffer 10 can be reduced.
Although, the circuit design of the input buffer 10 of the prior art can be provided with the compensation function for the time skew, however, it is just a qualitative compensation not a quantitatively exact compensation, and after compensating, the time skew is still unable to reach the range that the circuit can be allowed. Moreover, the present working voltage (VDD) becomes lower and lower, the operating range is smaller and smaller when the input buffer operates within the saturated area, such that the feedback compensation of the input buffer 10 is not easily commented.